The present invention relates to a level shift circuit that transmits a signal to a secondary system operated at an operating electric potential different from the operating electric potential on a primary side as an input side.
In a circuit such as a half-bridge circuit having switching devices connected in series and driven by a power supply in a high electric potential system, a level shift circuit is used for driving a switching device on the high electric potential system side by a signal on a low electric potential system side.
FIG. 4 is a circuit diagram showing an example of a configuration of a half-bridge circuit using a conventional level shift circuit. In FIG. 4, reference numeral 100 denotes an output circuit with a low electric potential side switching device SWL and a high electric potential side switching device SWH connected in series. The output circuit 100 is supplied with a voltage from a high voltage power supply Ein. The low electric potential side switching device SWL is a device such as an N-channel MOS transistor or an N-type IGBT (Insulated Gate Bipolar Transistor), and the high electric potential side switching device SWH is a device such as an N-channel or P-channel MOS transistor or a P-type or N-channel IGBT
Reference numeral 110 denotes a high electric potential side driving circuit formed of a level shift circuit, a driving device DRVH, carrying out on-off control of the high electric potential side switching device SWH by receiving the output of the level shift circuit, and a power supply E1. The level shift circuit is a section of the high electric potential side driving circuit 110 except the driving device DRVH and the power supply E1. Namely, the level shift circuit is formed of a series circuit of a resistor R1 and an N-channel MOS transistor MN1, a series circuit of a resistor R2 and an N-channel MOS transistor MN2, a flip-flop FF as a storage device, an inverter (inverting device) INV1 whose input side is connected to the connection point of the resistor R1 and the N-channel MOS transistor MN1 and whose output side is connected to a set input terminal S of the flip-flop FF, and an inverter INV2 whose input side is connected to the connection point of the resistor R2 and the N-channel MOS transistor MN2 and whose output side is connected to a reset input terminal R of the flip-flop FF.
A signal SH outputted from an output terminal Q of the flip-flop FF is inputted to the driving device DRVH as a signal subjected to level shifting by the level shift circuit. The output side of the driving device DRVH is connected to the gate terminal of the switching device SWH. The low electric potential side power supply terminals of the flip-flop FF, driving device DRVH and power supply E1 are connected to a connection point Vsw (hereinafter the electric potential of the connection point Vsw is also designated by Vsw) of the switching devices SWL and SWH, by which the flip-flop FF and the driving device DRVH receive supplies of power from the power supply E1. Moreover, an end of each of the series circuit of the resistor R1 and the N-channel MOS transistor MN1 and the series circuit of the resistor R2 and the N-channel MOS transistor MN2 is connected to a high electric potential side terminal of the power supply E1 and the other end of each thereof is connected to the ground potential (GND). To the gates of the N-channel MOS transistor MN1 and MN2, input signals PON and POFF as pulse signals are inputted, respectively, each of which is an input signal to the level shift circuit of the high electric potential side driving circuit 110.
Reference numeral 120 denotes a low electric potential side driving circuit formed of a driving device DRVL carrying out on-off control of the low electric potential side switching device SWL and a power supply E2. The driving device DRVL receives a supply of power from the power supply E2 to output a signal, to which a signal SL inputted to the driving device DRVL is amplified, to the gate terminal of the low electric potential side switching device SWL. With the circuit configuration, when the signal SL is a high level signal H (High), the low electric potential side switching device SWL is turned-on (conduction) and, when the signal SL is a low level signal L (Low), the low electric potential side switching device SWL is turned-off (interruption). In short, the signal SL is a signal directly instructing the turning-on and -off of the low electric potential side switching device SWL.
The input signals PON and POFF inputted to the high electric potential side driving circuit 110, different from the signal SL, are such signals that the input signal PON is a signal instructing the timing of the initiation of the turned-on period (termination of the turned-off period) of the high electric potential side switching device SWH and the input signal POFF is a signal instructing the timing of the initiation of the turned-off period (termination of the turned-on period) of the high electric potential side switching device SWH. FIG. 5 is a timing chart for illustrating a level shift operation in the half-bridge circuit shown in FIG. 4. The input signal PON becoming the high level signal H turns-on the N-channel MOS transistor MN1 to make the input signal of the inverter INV1 become a low level signal L and make the output signal become a high level signal H. This sets the flip-flop FF to provide the signal SH as the high level signal H, which makes the high electric potential side switching device SWH turned-on. Moreover, the input signal POFF becoming the high level signal H makes the N-channel MOS transistor MN2 turned-on to make the input signal of the inverter INV2 become a low level signal L and make the output signal become a high level signal H. This resets the flip-flop FF to provide the signal SH as the low level signal L, which makes the high electric potential side switching device SWH turned-off.
The switching devices SWL and SWH are complementary turned-on and -off (when the one is turned-on, the other is turned-off) except for their respective dead times in which both of them are turned-off. When the switching device SWL is turned-on, the electric potential Vsw at the connection point Vsw becomes the ground potential and, when the switching device SWH is turned-on, the electric potential Vsw at the connection point Vsw becomes equal to the output voltage Ein of the high voltage power supply Ein (the output voltage is also denoted by Ein).
A sign RL denotes a load that receives a supply of power from the half-bridge circuit. The load RL is connected between the connection point Vsw and the ground.
Here, consider the case when a state in which the switching device SWL is turned-on is switched to a state in which the switching device SWH is turned-on. At this time, the electric potential Vsw of the connection point Vsw is abruptly changed from the ground potential to an electric potential equal to the high voltage Ein. In an actual half-bridge circuit, between the connection point Vsw and the connection point of the resistor R1 and the N-channel MOS transistor MN1, a parasitic capacitance Cp11 is present, and between the connection point Vsw and the connection point of the resistor R2 and the N-channel MOS transistor MN2, a parasitic capacitance Cp21 is present. Moreover, between the connection point of the resistor R1 and the N-channel MOS transistor MN1 and the ground, a parasitic capacitance Cp12 is present and, between the connection point of the resistor R2 and the N-channel MOS transistor MN2 and the ground, parasitic capacitance Cp22 is also present.
With both of the N-channel MOS transistors MN1 and MN2 turned-off without the input signal PON and the input signal POFF being inputted, the change in the electric potential Vsw at the connection point Vsw from the ground potential to a high electric potential equal to the high voltage Ein causes a voltage to which a voltage equal to the electric potential change is divided by the impedances of the parasitic capacitances Cp11 and Cp12, to be applied to the connection point of the resistor R1 and the N-channel MOS transistor MN1 and causes a voltage to which a voltage equal to the electric potential change is divided by the impedances of the parasitic capacitances Cp21 and Cp22, to be applied to the connection point of the resistor R2 and the N-channel MOS transistor MN2. This produces an electric potential difference across each of the resistors R1 and R2. Namely, a false signal of a low level signal L is inputted to each of the inverters INV1 and INV2, which causes the simultaneous input of the set input signal and a reset input signal into the flip-flop FF. As a result, a problem occurs in that the output of the flip-flop FF becomes indeterminate, which may also cause the turning-on and -off of the switching device SWH to become indeterminate.
The phenomenon with a set input signal and a reset input signal simultaneously inputted to the flip-flop FF is called a dv/dt noise. The reason is as follows. Namely, with both of the N-channel MOS transistors MN1 and MN2 being turned-off, a change in the electric potential Vsw at the connection point Vsw to a higher electric potential causes both of the voltage across the parasitic capacitance Cp12 and the voltage across the parasitic capacitance Cp22 to increase by which electric charges in the parasitic capacitances Cp12 and Cp22 change to increase. The amounts of the increased electric charges in the parasitic capacitances Cp12 and Cp22 can be considered to be (partly) supplied by currents in the resistors R1 and R2, respectively. The values of the currents in the resistors R1 and R2 are equivalent to the amounts of changes with respect to the time in the electric charges in the parasitic capacitances Cp12 and Cp22, respectively, and the amount of change in electric charges with respect to time is to be proportional to dv/dt, the value of the derivative of the voltage across the capacitor with respect to time. Namely, this is because the phenomenon appears with the currents, whose values are proportional to the values of the derivative with respect to time dv/dt of the electric potential Vsw at the connection point Vsw, simultaneously flowing in the resistors R1 and R2. The phenomenon is, as shown in the later half (the right half) of an elapsed time in FIG. 5, equivalent to that in which the input signals PON and POFF simultaneously become high level signals H (in actual, none of the input signals become high level signals H). States of signals with respect to the half-bridge circuit using the conventional level shift circuit are shown in Table 1.
TABLE 1FFPONPOFFS InputR InputSHLLLLPrevious StateHLHLHLHLHLHHHHIndeterminate
The dv/dt noise has a possibility of directly relating to the big problem of causing the turning-on and -off of the switching device to be indeterminate. Thus, it is necessary to take measures against this.
In FIG. 6, the configuration of the power device driving circuit disclosed in Japanese Patent No. 3,429,937 is shown as a conventional art with respect to a measure against dv/dt noises. In FIG. 6, the same parts as those shown in FIG. 4 are denoted with the same reference numerals and signs with detailed explanations thereof omitted. The parasitic capacitances Cp11, Cp12, Cp21 and Cp22 are omitted to be shown in the drawing (the same in the following). The circuit shown in FIG. 6 differs from the circuit shown in FIG. 4 in that a protection circuit 200 is provided in a level shift circuit in a high electric potential side driving circuit 110A. When any one of the signals outputted from the two inverters INV1 and INV2 is inputted to the protection circuit 200 as a low level signal L, the protection circuit 200 transmits the output signals of the inverters INV1 and INV2 to the set terminal S and the reset terminals R, respectively, of the flip-flop FF as they are. Moreover, when both of the output signals of the inverters INV1 and INV2 are high level signals H, the protection circuit 200 outputs low level signals L to both of the set terminal S and the reset terminals R of the flip-flop FF to make the flip-flop FF keep the previous state so as to prevent the output of the flip-flop FF from becoming indeterminate. Thus, as shown in FIG. 7, a timing chart for illustrating the operation of the conventional power device driving circuit shown in FIG. 6, even when dv/dt noises are produced to cause a state equivalent to the state in which both of input signals PON and POFF become high level signals H, the protection circuit 200 makes the output of the flip-flop FF unchanged to keep the previous state, thereby preventing the output of the flip-flop FF from becoming indeterminate.
In FIGS. 8 and 9, two examples of circuit configurations are shown with respect to the conventional protection circuit 200. FIG. 8 is a circuit diagram showing a first example of the circuit configuration, in which inverters INV10 to INV16, a NOR gate NOR10, and NAND gates NAND10 and NAND 11 are provided. To the inverters INV10 and INV11, the outputs of the inverters INV1 and INV2 are inputted, respectively. The output sides of the INV15 and INV16 are connected to the set input terminal S and the reset input terminal R, respectively, of the flip-flop FF. In the circuit, with both of the output signals of the inverters INV1 and INV2 being high level signals H, the output signal of the NOR gate NOR10 becomes a high level signal H, and the output signal of the inverter INV 13 becomes a low level signal L. The outputted low level signal L is inputted to the NAND gates NAND10 and NAND 11, both of which therefore output high level signals H, to make both of the output signals of the inverters INV15 and INV16 become low level signals L, which are inputted to the set input terminal S and the reset input terminal R. On the other hand, when either one of the input signal PON or POFF becomes a low level signal L, the output of one of the inverters INV1 and INV2 becomes a low level signal L to make the output of the NOR gate NOR10 provide a low level signal L, by which the output of the inverter INV13 becomes a high level signal H. Thus, the outputs of the inverters INV15 and INV16 become equal to the outputs of the inverters INV1 and INV2, respectively.
FIG. 9 is a circuit diagram showing a second example of the circuit configuration of the conventional protection circuit 200, which has inverters INV20 to INV22, NOR gates NOR20 and NOR21, and a NAND gate NAND20. The output of the inverter INV1 is inputted to the inverter INV20 and one of input terminals of the NAND gate NAND20, and the output of the inverter INV2 is inputted to the inverter INV 22 and the other input terminal of the NAND gate NAND20. The output sides of the NOR gates NOR20 and NOR 21 are connected to the set input terminal S and the reset input terminal R, respectively, of the flip-flop FF. In the circuit, with both of the outputs of the inverters INV1 and INV2 being high level signals H, the output of the NAND gate NAND20 becomes a low level signal L and the output of the inverter INV21 therefore becomes a high level signal H, which is inputted to the NOR gates NOR20 and NOR21. Therefore, both of the outputs of the NOR gates NOR20 and NOR21 to be inputted to the set input terminal S and the reset input terminal R, respectively, become low level signals L. On the other hand, with either one of the output of the inverter INV1 or INV2 being a low level signal L, the output of the NAND circuit NAND20 becomes a high level signal H to make the output of the inverter INV21 become a low level signal L. Thus, the outputs of the NOR gates NOR20 and NOR21 become equal to the outputs of the inverters INV1 and INV2, respectively. In addition, states of signals with respect to the power device driving circuit disclosed in Japanese Patent No. 3,429,937 shown in FIG. 6 are shown in Table 2.
TABLE 2FFPONPOFFS InputR InputSHLLLLPrevious StateHLHLHLHLHLHHLLPrevious State    Patent Document 1: Japanese Patent No. 3,429,937
In the protection circuit 200, before the outputs of the inverters INV1 and INV2 are transmitted to the set input terminal S and the reset input terminal R, respectively, of the flip-flop FF through the protection circuit 200, it is necessary to detect that both of the outputs of the inverters INV1 and INV2 are high level signals H and to block them. Otherwise, the high level signals H of the outputs of the inverters INV1 and INV2 would pass through the protection circuit 200 to be transmitted to the flip-flop FF. Accordingly, in the circuit shown in FIG. 8, before the inverters INV12 and INV14 responds to the outputs of the inverters INV1 and INV2, respectively, the inverter INV13 must respond to the outputs. In the circuit shown in FIG. 9, before the inverters INV20 and INV22 responds to the outputs of the inverters INV1 and INV2, respectively, the inverter INV21 must respond to the outputs. In the circuit shown in FIG. 8, there is a difference in the number of gate stages, through which a signal (an output signal of the inverter INV1 or the inverter INV 2) passes, between a signal path through the inverter INV12 (or the inverter INV14) and a signal path through the NOR gate NOR10 and the inverter INV13. In the circuit shown in FIG. 9, there is a difference in the number of gate stages, through which a signal (an output signal of the inverter INV1 or the inverter INV 2) passes, between a signal path through the inverter INV20 (or the inverter INV22) and a signal path through the NAND gate 20 and the inverter INV21. Thus, for ensuring the foregoing, delay times of the inverters INV12, INV14, INV20 and INV22 must be deliberately lengthened (for example, in the circuit shown in FIG. 8, the independent delay time of each of the inverter INV12 and the inverter INV14 must be made longer than the sum of the delay times of both of the NOR gate NOR10 and the inverter INV13).
On the other hand, when a half-bridge circuit is applied to a circuit such as a switching power supply circuit, because of the recent progress in the switching speed, high-speed switching requires more precise control of the time of turning-on and -off of a switching device in one period. Thus, lengthening the delay time of the inverters INV12, INV1, INV20 and INV22 is against the progress, which makes the high-speed switching difficult.
Accordingly, the object of the invention is to solve the foregoing problem and provide a level shift circuit which can take a measure against dv/dt noises without causing unnecessary delay in turning-on and -off control of a switching device.
Further objects and advantages of the invention will be apparent from the following description of the invention.